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sa8027 2.5 ghz low voltage, low power rf fractional-n/if integer frequency synthesizer product data supersedes data of 2001 jul 18 2001 aug 21 integrated circuits
philips semiconductors product data sa8027 2.5 ghz low voltage, low power rf fractional-n/if integer frequency synthesizer 2 2001 aug 21 8532244 26947 general description the sa8027 bicmos device integrates programmable dividers, charge pumps and phase comparators to implement phase-locked loops. the device is designed to operate from 3 nicd cells, in pocket phones, with low current and nominal 3 v supplies. the synthesizer operates at vco input frequencies up to 2.5 ghz. the synthesizer has fully programmable main, auxiliary and reference dividers. all divider ratios are supplied via a 3-wire serial programming bus. the main divider is a fractional-n divider with programmable integer ratios from 512 to 65535. separate power and ground pins are provided to the charge pumps and digital circuits. the ground pins should be externally connected to prevent large currents from flowing across the die and causing damage. v ddcp must be equal to or greater than v dd . the charge pump current (gain) is fully programmable, while i set is set by an external resistance at the r set pin (refer to section 1.5, main output charge pumps and fractional compensation currents) . the phase/frequency detector charge pump outputs allow for implementing a passive loop filter. features ? low phase noise ? low power ? fully programmable main and auxiliary dividers ? programmable normal & integral charge pumps outputs ? fast locking adaptive mode design ? internal fractional spurious compensation ? hardware and software power down ? split supply for v dd and v ddcp ? loop filter bandwidth programmability applications ? 500 to 2500 mhz wireless equipment ? cellular phones (all standards) ? wlan ? portable battery-powered radio equipment. sr01649 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 20 lock test v dd gnd rfin+ rfin gnd cp php phi gnd cp pon strobe data clock refin+ refin r set auxin v ddcp pha 10 figure 1. tssop20 pin configuration 13 7 2 3 4 5 6 top view 1 8 9 10 11 12 14 15 16 17 18 19 20 21 22 23 24 clock refin+ refin sr02176 n/c v ddpre gnd gnd pre rfin+ rfin gnd cp php phi gnd pha auxin n/c data strobe pon lock test v dd cp v ddcp r set figure 2. hbcc24 pin configuration quick reference data symbol parameter conditions min. typ. max. unit v dd supply voltage 2.7 3.6 v v ddcp analog supply voltage v ddcp v dd 2.7 3.6 v i ddcp +i dd supply current main and aux. on 7.7 ma i ddcp +i dd total supply current in power-down mode 1 m a f vco input frequency 500 2500 mhz f aux input frequency 100 550 mhz f ref crystal reference input frequency 5 40 mhz f pc maximum phase comparator frequency 4 mhz t amb operating ambient temperature 40 +85 c ordering information type number package type number name description version sa8027dh tssop20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 SA8027W hbcc24 plastic, heatsink bottom chip carrier; 24 terminals; body 4 x 4 x 0.65 mm (note 1) sot564-1 note: 1. the SA8027W will be released for production q2, 2001.
philips semiconductors product data sa8027 2.5 ghz low voltage, low power rf fractional-n/if integer frequency synthesizer 2001 aug 21 3 v dd sr02357 clock data strobe rf/mainin+ rf/mainin refin+ refin if/auxin test load signals address decoder 2bit shift register 22bit shift register control latch latch main divider sm reference divider 2222 latch amp amp 15 16 6 5 19 18 17 12 2 latch aux divider phase detector phase detector frac comp pump bias pump current setting 13 v ddcp gnd 4 sa 7, 10 3 gnd cp r set php phi lock pha 14 8 9 1 11 pon 20 lock select figure 3. block diagram (tssop20) tssop20 pin description symbol pin description lock 1 lock detect output test 2 test (should be either grounded or connected to v dd ) v dd 3 digital supply gnd 4 digital ground rfin+ 5 rf input to main divider rfin 6 rf input to main divider gnd cp 7 charge pump ground php 8 main normal charge pump phi 9 main integral charge pump gnd cp 10 charge pump ground symbol pin description pha 11 auxiliary charge pump output auxin 12 input to auxiliary divider v ddcp 13 charge pump supply voltage r set 14 external resistor from this pin to ground sets the charge pump current refin 15 reference input refin+ 16 reference input clock 17 programming bus clock input data 18 programming bus data input strobe 19 programming bus enable input pon 20 power down control
philips semiconductors product data sa8027 2.5 ghz low voltage, low power rf fractional-n/if integer frequency synthesizer 2001 aug 21 4 v dd sr02358 clock data strobe rf/mainin+ rf/mainin refin+ refin if/auxin test load signals address decoder 2bit shift register 22bit shift register control latch latch main divider sm reference divider 2222 latch amp amp 16 17 5 4 20 19 18 11 23 latch aux divider phase detector phase detector pump bias pump current setting 14 v ddcp gnd pre 3 sa 6, 9 24 gnd cp r set php phi lock pha 15 7 8 22 10 pon 21 gnd 2 v ddpre 1 lock select frac comp figure 4. block diagram (hbcc24) hbcc24 pin description symbol pin description v ddpre 1 prescaler supply voltage gnd 2 digital ground gnd pre 3 prescaler ground rfin+ 4 rf input to main divider rfin 5 rf input to main divider gnd cp 6 charge pump ground php 7 main normal charge pump phi 8 main integral charge pump gnd cp 9 charge pump ground pha 10 auxiliary charge pump output auxin 11 input to auxiliary divider n/c 12 not connected n/c 13 not connected symbol pin description v ddcp 14 charge pump supply voltage r set 15 external resistor from this pin to ground sets the charge pump current refin 16 reference input refin+ 17 reference input clock 18 programming bus clock input data 19 programming bus data input strobe 20 programming bus enable input pon 21 power down control lock 22 lock detect output test 23 test (should be either grounded or connected to v dd ) v dd 24 digital supply
philips semiconductors product data sa8027 2.5 ghz low voltage, low power rf fractional-n/if integer frequency synthesizer 2001 aug 21 5 limiting values symbol parameter min. max. unit v dd digital supply voltage 0.3 +3.6 v v ddcp analog supply voltage 0.3 +3.6 v d (v ddcp v dd ) difference in voltage between v ddcp and v dd (v ddcp v dd ) 0.3 +0.9 v vi n all input pins 0.3 v dd + 0.3 v d v gnd difference in voltage between gnd cp and gnd (these pins should be connected together) 0.3 +0.3 v t stg storage temperature 55 +125 c t amb operating ambient temperature 40 +85 c t j maximum junction temperature 150 c thermal characteristics symbol parameter value unit r th ja thermal resistance from junction to ambient in free air 135 k/w
philips semiconductors product data sa8027 2.5 ghz low voltage, low power rf fractional-n/if integer frequency synthesizer 2001 aug 21 6 characteristics v ddcp = v dd = +3.0 v, t amb = +25 c; unless otherwise specified. symbol parameter conditions min. typ. max. unit supply v dd digital supply voltage 2.7 3.6 v v ddcp analog supply voltage v ddcp v dd 2.7 3.6 v i total synthesizer operational supply current v dd = +3.0 v (with main and aux on) 7.7 ma i standby total supply current in power-down mode logic levels 0 or v dd 1 m a rfin main divider input f vco vco input frequency 500 2500 mhz v rfin ac-coupled input signal level r in (external) = r s = 50 w ; sin g le-ended drive; 18 0 dbm g max. limit is indicative @ 500 to 2500 mhz 80 632 mv pp z rfin input impedance (real part) f vco = 2.4 ghz 300 w c rfin typical pin input capacitance f vco = 2.4 ghz 1 pf n main main divider ratio 512 65535 f pcmax maximum loop comparison frequency indicative, not tested 4 mhz aux divider input f auxin input frequency range 100 550 mhz v ac cou p led in p ut signal level r in (external) = r s = 50 w ; 15 0 dbm v auxin ac - co u pled inp u t signal le v el in () s max. limit is indicative 112 632 mv pp z auxin input impedance (real part) f vco = 500 mhz 3.9 k w c auxin typical pin input capacitance f vco = 500 mhz 0.5 pf n aux auxiliary division ratio 128 16383 reference divider input f refin input frequency range from tcxo 5 40 mhz v refin ac-coupled input signal level single-ended drive; max. limit is indicative 360 1300 mv pp z refin input impedance (real part) f ref = 20 mhz 10 k w c refin typical pin input capacitance f ref = 20 mhz 1 pf r ref reference division ratio sa = sm = o000o 4 1023 charge pump current setting resistor input r set external resistor from pin to ground 6 7.5 15 k w v set regulated voltage at pin r set = 7.5 k w 1.22 v charge pump outputs; r set = 7.5 k w i cp charge pump current ratio to i set 1 current gain = i ph /i set 15 +15 % i match sink-to-source current matching v ph = 1/2 v ddcp 10 +10 % i zout output current variation versus v ph 2 v ph in compliance range 10 +10 % i lph charge pump off leakage current v ph = 1/2 v ddcp 10 +10 na v ph charge pump voltage compliance 0.6 v ddcp 0.7 v
philips semiconductors product data sa8027 2.5 ghz low voltage, low power rf fractional-n/if integer frequency synthesizer 2001 aug 21 7 characteristics (continued) symbol parameter conditions min. typ. max. unit phase noise (condition r set = 7.5 k w , cp = 00) synthesizer's contribution to close-in phase noise of 900 mhz rf signal at 1 khz offset. gsm f ref = 13mhz, tcxo, 90 dbc/hz synthesizer's contribution to close-in phase noise of 1800 mhz rf signal at 1 khz offset. f ref = 13mhz , tcxo , f comp = 1mhz indicative, not tested 83 dbc/hz (f) synthesizer's contribution to close-in phase noise of 800 mhz rf signal at 1 khz offset. tdma f ref = 19.44mhz, tcxo, 85 dbc/hz synthesizer's contribution to close-in phase noise of 2100 mhz rf signal at 1 khz offset. f ref = 19 . 44mhz , tcxo , f comp = 240khz indicative, not tested 77 dbc/hz interface logic input signal levels v ih high level input voltage 0.7*v dd v dd +0.3 v v il low level input voltage 0.3 0.3*v dd v i leak input leakage current logic 1 or logic 0 0.5 +0.5 m a lock detect output signal (in push/pull mode) v ol low level output voltage i sink = 2 ma 0.4 v v oh high level output voltage i source = 2 ma v dd 0.4 v notes: 1. i set v set r set bias current for charge pumps 2. the relative output current variation is defined as: i out i out 2 (i 2 i 1 ) |i 2 i 1 | ; with i 1 @v 1 0.6 v, i 2 @v 2 v ddcp 0.7 v (see figure 5.) i 2 i 1 i 2 i 1 v 1 v 2 current v ph sr00602 i zout voltage figure 5. relative output current variation
philips semiconductors product data sa8027 2.5 ghz low voltage, low power rf fractional-n/if integer frequency synthesizer 2001 aug 21 8 1.0 functional description 1.1 main fractional-n divider the rfin inputs drive a pre-amplifier to provide the clock to the first divider stage. for single ended operation, the signal should be fed to one of the inputs while the other one is ac grounded. the pre-amplifier has a high input impedance, dominated by pin and pad capacitance. the circuit operates with signal levels from 18 dbm to 0 dbm, and at frequencies as high as 2.5 ghz. the divider consists of a fully programmable bipolar prescaler followed by a cmos counter. total divide ratios range from 512 to 65535. the fractional modulus is selected by programming fmod in the a word. there are 2 modulus to select from: when fmod = 0, modulo 8 is selected; when fmod = 1, modulo 5 is selected. at the completion of a main divider cycle, a main divider output pulse is generated which will drive the main phase comparator. also, the fractional accumulator is incremented by the value of nf. the accumulator works with modulo set by fmod. when the accumulator overflows, the overall division ratio n will be increased by 1, to n + 1. the average division ratio over modulo main divider cycles (either 5 or 8) will be nfrac n nf f mod the output of the main divider will be modulated with a fractional phase ripple. the phase ripple is proportional to the contents of the fractional accumulator and is nulled by the fractional compensation charge pump. thus, f vco = f comp * n nf f mod . the reloading of a new main divider ratio is synchronized to the state of the main divider to avoid introducing a phase disturbance. 1.2 auxiliary divider the auxin input drives a pre-amplifier to provide the clock to the first divider stage. the pre-amplifier has a high input impedance, dominated by pin and pad capacitance. the circuit operates with signal levels from 15 dbm to 0 dbm (112 to 632 mvpp), and at frequencies as high as 550 mhz. the divider consists of a fully programmable bipolar prescaler followed by a cmos counter. total divide ratios range from 128 to 16383. 1.3 reference divider the reference divider consists of a divider with programmable values between 4 and 1023 followed by a three bit binary counter. the 3 bit sm (sa) register (see figure 6) determines which one of the 5 output pulses are selected as the main (auxiliary) phase detector input, thus allowing the main pfd and auxiliary pfd to operate at different frequencies. 1.4 phase detector (see figure 7) the reference and main (aux) divider outputs are connected to a phase/frequency detector that controls the charge pump. the pump current is set by an external resistor in conjunction with control bits cp0 and cp1 in the c-word (see table 1). the dead zone (caused by finite time taken to switch the current sources on or off) is cancelled by forcing the pumps on for a minimum time ( t ) at every cycle (backlash time) providing improved linearity. sr01415 divide by r /2 /2 /2 /2 reference input sm=o000o sm=o001o sm=o010o sm=o011o sm=o100o sa=o100o sa=o011o sa=o010o sa=o001o sa=o000o to main phase detector to auxiliary phase detector figure 6. reference divider
philips semiconductors product data sa8027 2.5 ghz low voltage, low power rf fractional-n/if integer frequency synthesizer 2001 aug 21 9 sr01451 r x p n ref divider aux/main divider d q clk a1o r d r clk a1o x q n p t v cc i ph gnd ptype charge pump ntype charge pump r f ref f ref i ph t t figure 7. phase detector structure with timing
philips semiconductors product data sa8027 2.5 ghz low voltage, low power rf fractional-n/if integer frequency synthesizer 2001 aug 21 10 1.5 main output charge pumps and fractional compensation currents (see figure 8) the main charge pumps on pins php and phi are driven by the main phase detector and the charge pump current values are determined by the current at pin r set in conjunction with bits cp0, cp1 in the c-word (see table 1). the main charge pumps will enter speed up mode after the a-word is set and strobe goes high. when strobe goes low, charge pump will exit speed up mode. the fractional compensation is derived from the current at r set , the contents of the fractional accumulator (frd) and by the program value of the fdac. the timing for the fractional compensation is derived from the main divider. 1.6 principle of fractional compensation the fractional compensation is designed into the circuit as a means of reducing or eliminating fractional spurs that are caused by the fractional phase ripple of the main divider. if i comp is the compensation current and i pump is the pump current, then for each charge pump: i pump_total = i pump + i comp . the compensation is done by sourcing a small current, i comp , see figure 9, that is proportional to the fractional error phase. for proper fractional compensation, the area of the fractional compensation current pulse must be equal to the area of the fractional charge pump ripple. the width of the fractional compensation pulse is fixed to 128 vco cycles, the amplitude is proportional to the fractional accumulator value and is adjusted by fdac values (bits fc70 in the b-word). the fractional compensation current is derived from the main charge pump in that it follows all the current scaling through external resistor setting, r set , programming or speed-up operation. for a given charge pump, i comp = ( i pump / 128 ) * ( fdac / 5*128) * frd frd is the fractional accumulator value and is automatically updated. the theoretical values for fdac are: 128 for fmod = 1 (modulo 5) and 80 for fmod = 0 (modulo 8). sr02359 reference r main m divide ratio charge pump output accumulator value (frd) fractional compensation current (i comp ) i pumptotal n n n+1 n n+1 241 3 0 pulse width modulation pulse level modulation ma m a graphs not to scale. note: for a proper fractional compensation, the area of the fractional compensation current pulse must be equal to the area of the ch arge pump output. figure 8. waveforms for nf = 2 modulo 5 fraction = 2 / 5 sr01800 f rf main divider fractional accumulator f ref i comp i pump loop filter & vco s figure 9. current injection concept
philips semiconductors product data sa8027 2.5 ghz low voltage, low power rf fractional-n/if integer frequency synthesizer 2001 aug 21 11 1.7 charge pumps the php and phi charge pumps are driven by the main phase detector, while the pha charge pump is driven by the auxiliary phase detector. the i set value (refer to table 1) is determined by the external resistor attached to the r set pin. the charge pump, by default, will automatically go into speed-up mode (which can deliver up to 15*i set for php_su, and 36*i set for phi), based on the strobe pulse width following the a word, to reduce switching speed for large tuning voltage steps (i.e., large frequency steps). figure 10 shows the recommended passive loop filter configuration. note: this charge pump architecture eliminates the need for added active switches and reduces external component count. furthermore, the programmable charge pump gains provide some programmability to the loop filter bandwidth. the duration of speed-up mode is determined by the strobe pulse width following the a word. recommended optimal strobe width is equal to the total loop filter capacitance charge time from state 1 to state 2. the strobe width must not exceed this charge time. the strobe width is controlled by the cpu ( number of clock cycles). in addition, charge pumps will stay in speed-up mode continuously while tspu = 1 (in d word). the speed-up mode can also be disabled by programming t dis-spu = 1 (in d word). sr02356 vco c3 c2 r2 c1 r1 php[phpsu] phi figure 10. typical passive 3-pole loop filter table 1. main and auxiliary charge pump currents cp1 cp0 i pha i php i phpsu i phi 0 0 1.5xl set 3xi set 15xl set 36xl set 0 1 0.5xl set 1xl set 5xl set 12xl set 1 0 1.5xl set 3xl set 15xl set 0 1 1 0.5xl set 1xl set 5xl set 0 notes: 1. i set = v set /r set : bias current for charge pumps. 2. cp1 is used to disable the phi pump, i phpsu is the total current at pin php during speed up condition. 1.8 lock detect the output lock maintains a logic `1' when the auxiliary phase detector (and/ored) with the main phase detector indicates a lock condition. the lock condition for the main and auxiliary synthesizers is defined as a phase difference of less than 1 period of the frequency at the input ref in+, . one counter can fulfill the lock condition when the other counter is powered down. out of lock (logic `0') is indicated when both counters are powered down. 1.9 power-down mode the power-down signal can be either hardware (pon) or software (pd). the pon signal is exclusively ored with the pd bits in b-word. if pon = 0, then the part is powered up when pd = 1. pon can be used to invert the polarity of the software bit pd. when the synthesizer is reactivated after power-down, the main and reference dividers are synchronized to avoid possibility of random phase errors on power-up.
philips semiconductors product data sa8027 2.5 ghz low voltage, low power rf fractional-n/if integer frequency synthesizer 2001 aug 21 12 2.0 serial programming bus the serial input is a 3-wire input (clock, strobe, data) to program all counter divide ratios, fractional compensation dac, selection and enable bits. the programming data is structured into 24 bit words; each word includes 2 or 3 address bits. figure 11 shows the timing diagram of the serial input. when the strobe goes active high, the clock is disabled and the data in the shift register remains unchanged. depending on the address bits, the data is latched into the selected working registers or temporary registers. in order to fully program the synthesizer, 3 words must be sent: c, b, and a, in that order. a typical programming sequence is illustrated in figure 12. table 2 shows the format and the contents of each word. the d word is used for testing purposes and should be initially set to 0 for normal operation. when sending the b-word, data bits fc70 for the fractional compensation dac are not loaded immediately. instead they are stored in temporary registers. only when the a-word is loaded, these temporary registers are loaded together with the main divider ratio. 2.1 serial bus timing characteristics (see figure 11) v dd = v ddcp =+3.0 v; t amb = +25 c unless otherwise specified. symbol parameter min. typ. max. unit serial programming clock; clk t r input rise time 10 40 ns t f input fall time 10 40 ns t cy clock period 100 ns enable programming; strobe t start delay to rising clock edge 40 ns t w minimum inactive pulse width 1/f comp ns t su;e enable set-up time to next clock edge 20 ns register serial input data; data t su;dat input data to clock set-up time 20 ns t hd;dat input data to clock hold time 20 ns application information sr01417 clk data strobe lsb address t su;dat t hd;dat t f t w t r t su;e t start t cy msb 0 figure 11. serial bus timing diagram
philips semiconductors product data sa8027 2.5 ghz low voltage, low power rf fractional-n/if integer frequency synthesizer 2001 aug 21 13 sr02360 poweron program c word select sa, sm set charge pump gain set aux divider program b word select fdac set power-up option set lock detect set ref divider program a word select main divider set fractional-n set fmod ready to operate change main frequency change fdac change aux frequency power down power up power off y y y n n n n n program c word program b word program b word y program d word set default y program a word figure 12. typical programming sequence
philips semiconductors product data sa8027 2.5 ghz low voltage, low power rf fractional-n/if integer frequency synthesizer 2001 aug 21 14 data format table 2. format of programmed data last in msb serial programming format first in lsb p23 p22 p21 p20 ../.. ../.. p1 p0 table 3. a word, length 24 bits last in msb lsb first in address fmod fractional-n main divider ratio spare 0 0 fmod nf2 nf1 nf0 n15 n14 n13 n12 n11 n10 n9 n8 n7 n6 n5 n4 n3 n2 n1 n0 sk1 sk2 default 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 a word address fixed to 00. fractional modulus select fmod = 0 is modulo 8; fmod = 1 is modulo 5. fractional-n increment fractional-n increment values 000 to 111 (0 to 7). nf is a 3-bit word. n-divider n0..n15, main divider values 512 to 65535 allowed for divider ratio. spare sk1, sk2 must be set to 0. table 4. b word, length 24 bits address reference divider lock pd fdac (fractional compensation dac) 0 1 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 l1 l0 main aux fc7 fc6 fc5 fc4 fc3 fc2 fc1 fc0 default 0 0 0 1 0 1 0 0 0 1 0 0 1 1 0 1 0 1 0 0 0 0 b word address fixed to 01 ref-divider r0..r9, reference divider values 4 to 1023 allowed for divider ratio. r <9:0>. lock detect output l1 l0 0 0 combined main, aux. lock detect signal present at the lock pin (push/pull). 0 1 combined main, aux, lock detect signal present at the lock pin (open drain). 1 0 main lock detect signal present at the lock pin (push/pull). 1 1 auxiliary loop lock detect signal present at the lock pin (push/pull). when auxiliary loop and main loop are in power down mode, the lock indicator is low. power down (pd) pon pin is tied to gnd main = 1: power-on to main pll. main = 0: power-down to main pll. aux = 1: power-on to aux pll. aux = 0: power-down to aux pll. pon pin is tied to v dd main = 0: power-on to main pll. main = 1: power-down to main pll. aux = 0: power-on to aux pll. aux = 1: power-down to aux pll. fractional compensation fc7..0 fractional compensation charge pump current dac, values 0 to 255. table 5. c word, length 24 bits address auxiliary divider cp sm sa 1 0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 cp1 cp0 sm2 sm1 sm0 sa2 sa1 sa0 default 0 0 0 0 0 1 1 1 0 0 1 0 1 0 1 1 0 0 0 0 0 0 c word address fixed to 10 a-divider a0..a13, auxiliary divider values 128 to 16383 allowed for divider ratio. charge pump current ratio cp1, cp0: charge pump current ratio, see table 1. main comparison select sm comparison divider select for main phase detector. aux comparison select sa comparison divider select for auxiliary phase detector. table 6. d word, length 24 bits address synthesizer test bits 1 1 0 t dis-spu tspu default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 d word address fixed to 110. t dis-spu = 1 speed-up mode disabled. note : all other test bits must be set to 0 for normal operation. t spu = 1 speed-up mode always on. note : all other test bits must be set to 0 for normal operation.
philips semiconductors product data sa8027 2.5 ghz low voltage, low power rf fractional-n/if integer frequency synthesizer 2001 aug 21 15 typical performance characteristics sr02331 compliance voltage(v) icp (ua) 3000 2000 1000 0 1000 2000 3000 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 i set = 204 m a i set = 164 m a i set = 81 m a i set = 164 m a i set = 204 m a i set = 81 m a figure 13. phi charge pump output vs. i set (cp = 01_12x; temp = 25 c) sr02332 ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ?? ? ? ?? ? ? ?? ? ? ?? ? ? ?? ? ? ?? ? ?? ? ? ?? ? ? ?? ? ? ?? ? ? ?? ? ?? ? ? ? ?? ? ? ?? ? ?? ? ? ?? ? ? ?? ? ? ?? ? ? ?? ? ? ? ? ? ? ? ? ? ?? ?? ? ? ? ? ? ? ? ? ? 2000 1000 0 1000 2000 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 compliance voltage (v) icp (ua) 3000 3000 ?? 40 c +25 c +85 c figure 14. phi charge pump output vs. temperature (cp = 01_12x; v dd = 3.0 v; i set = 164 a) sr02333 8000 6000 4000 2000 0 2000 4000 6000 8000 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 i set = 164 m a i set = 204 m a i set = 204 m a i set = 164 m a i set = 81 m a compliance voltage (v) icp (ua) i set = 81 m a figure 15. phi charge pump output vs. i set (cp = 00_36x; temp = 25 c) sr02334 ? ? ? ? ? ? ? ? ?? ?? ? ? ? ? ? ?? ? ? ?? ? ? ?? ? ? ?? ? ?? ? ? ?? ? ? ?? ? ? ?? ? ? ?? ? ?? ? ? ?? ?? ? ?? ? ? ?? ? ?? ? ? ?? ? ? ?? ? ? ?? ? ? ?? ? ?? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? 8000 6000 4000 2000 0 2000 4000 6000 8000 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 icp (ua) ?? compliance voltage (v) 40 c +25 c +85 c figure 16. phi charge pump output vs. temperature (cp = 00_36x; v dd = 3.0 v; i set = 164 a) sr02335 800 600 400 200 0 200 400 600 800 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 compliance voltage i set = 204 m a i set = 164 m a i set = 81 m a i set = 204 m a icp (ua) i set = 164 m a i set = 81 m a figure 17. php charge pump output vs. i set (cp = 10_3x; v dd = 3.0 v; temp = 25 c) sr02336 icp (ua) compliance voltage (v) ? ? ? ? ? ?? ?? ? ? ? ? ? ? ?? ? ? ?? ? ?? ? ? ? ?? ? ? ?? ? ? ?? ? ?? ? ? ?? ? ? ?? ? ?? ? ?? ? ? ?? ? ? ? ?? ? ?? ? ? ?? ? ? ?? ? ? ?? ? ?? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ?? ?? ?? ? ? ? 600 400 200 0 200 400 600 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 800 800 ?? 40 c +25 c +85 c figure 18. php charge pump output vs. temperature (cp = 10_3x; v dd = 3.0 v; i set = 164 a)
philips semiconductors product data sa8027 2.5 ghz low voltage, low power rf fractional-n/if integer frequency synthesizer 2001 aug 21 16 typical performance characteristics (continued) sr02337 250 200 150 100 50 0 50 100 150 200 250 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 i set = 204 m a i set = 164 m a i set = 81 m a i set = 204 m a i set = 164 m a i set = 81 m a compliance voltage (v) icp (ua) figure 19. php charge pump output vs. i set (cp = 11_1x; v dd = 3.0 v; temp = 25 c) sr02338 icp (ua) compliance voltage (v) ?? ?? ?? ? ? ? ? ? ? ? ? ? ?? ?? ? ? ? ? ? ? ? ? ?? ?? ? ? ?? ?? ? ? ? ? ? ? ?? ?? ? ? ? ? ?? ?? ? ? ? ? ?? ?? ? ? ? ? ? ? ?? ? ? ? ?? ? ?? ?? ? ? ?? ? ? ?? ?? ?? ? ?? ? ? ? ?? ? ?? ? ? ? ?? ? ? ?? ? ? ?? ? ? ?? ?? ? ? ? ?? ? ?? ?? ? ? ? ? ? ? ?? ?? ? ? ? ? ? ? ? ? ? ? ? 200 150 100 50 0 50 100 150 200 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 ?? 40 c +25 c +85 c 250 250 figure 20. php charge pump output vs. temperature (cp = 11_1x; v dd = 3.0 v; i set = 164 a) sr02339 1500 1000 500 0 500 1000 1500 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 i set = 204 m a i set = 81 m a i set = 204 m a i set = 164 m a i set = 81 m a compliance voltage (v) icp (ua) i set = 164 m a figure 21. phpsu charge pump output vs. i set (cp = 01_5x; v dd = 3.0 v; temp = 25 c) sr02340 icp (ua) compliance voltage (v) ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ?? ? ? ?? ? ? ?? ? ? ?? ? ?? ? ? ?? ? ? ?? ? ? ?? ? ? ?? ? ?? ? ? ?? ? ? ?? ? ? ?? ? ? ?? ? ? ?? ? ?? ? ? ?? ? ? ?? ? ? ?? ? ? ? ? ? ?? ?? ? ? ? ? ? ? ? ? ? ? ? ? 1000 500 0 500 1000 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 ?? 40 c +25 c +85 c 1500 1500 figure 22. phpsu charge pump output vs. temperature (cp = 01_5x; v dd = 3.0 v; i set = 164 a) sr02341 icp (ua) compliance voltage (v) 4000 3000 2000 1000 0 1000 2000 3000 4000 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 i set = 204 m a i set = 81 m a i set = 204 m a i set = 164 m a i set = 81 m a i set = 164 m a figure 23. phpsu charge pump output vs. i set (cp = 00_15x; v dd = 3.0 v; temp = 25 c) sr02342 icp (ua) compliance voltage (v) ? ? ? ? ?? ?? ?? ?? ? ? ? ? ? ? ?? ?? ? ? ?? ? ? ? ?? ? ? ?? ? ? ? ?? ? ? ?? ? ?? ?? ? ? ?? ? ? ? ?? ? ? ? ?? ? ?? ?? ? ? ?? ? ? ?? ? ? ?? ? ? ? ?? ? ? ?? ? ? ?? ?? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ?? ? 3000 2000 1000 0 1000 2000 3000 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 ?? 40 c +25 c +85 c 4000 4000 figure 24. phpsu charge pump output vs. temperature (cp = 00_15x; v dd = 3.0 v; i set = 164 a)
philips semiconductors product data sa8027 2.5 ghz low voltage, low power rf fractional-n/if integer frequency synthesizer 2001 aug 21 17 typical performance characteristics (continued) sr02343 icp (ua) compliance voltage (v) 150 100 50 0 50 100 150 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 i set = 204 m a i set = 81 m a i set = 204 m a i set = 164 m a i set = 81 m a i set = 164 m a figure 25. pha charge pump output vs. i set (cp = 11_0.5x; temp = 25 c) sr02344 icp (ua) compliance voltage (v) ?? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ?? ? ?? ? ? ?? ? ? ?? ? ? ? ?? ? ?? ?? ? ?? ? ? ?? ? ? ?? ? ? ? ?? ?? ? ?? ? ? ? ?? ? ?? ? ? ?? ? ?? ? ? ? ?? ? ?? ?? ? ? ?? ? ? ?? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? 100 50 0 50 100 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 150 100 ?? 40 c +25 c +85 c figure 26. pha charge pump output vs. temperature (cp = 11_0.5x; v dd = 3.0 v; i set = 164 a) sr02346 icp (ua) 400 300 200 100 0 100 200 300 400 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 i set = 204 m a i set = 81 m a i set = 204 m a i set = 164 m a i set = 81 m a i set = 164 m a compliance voltage (v) figure 27. pha charge pump output vs. i set (cp = 10_1.5x; v dd = 3.0 v; temp = 25 c) sr02345 icp (ua) compliance voltage (v) ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ?? ? ? ?? ?? ? ? ?? ? ? ?? ? ?? ? ? ? ?? ? ? ?? ? ? ?? ? ? ?? ? ? ?? ? ? ?? ? ? ?? ? ?? ?? ? ? ?? ? ? ?? ? ? ?? ? ? ? ?? ? ?? ? ? ? ?? ? ? ? ? ? ? ? ? ?? ?? ? ? ? ? ? ? ? ? ? 300 200 100 0 100 200 300 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 ?? 40 c +25 c +85 c 400 400 figure 28. pha charge pump output vs. temperature (cp = 10_1.5x; v dd = 3.0 v; i set = 164 a) sr02347 51 48 45 42 39 36 33 30 27 24 21 18 15 12 9 6 3 0 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 2.6v 3.0v 3.6v input frequency (mhz) minimum signal input level (dbm) figure 29. main divider input sensitivity vs. frequency and supply voltage (temp = 25 c; i set = 164 m a; nf = 0; mod = 8; n = 853) sr02348 minimum signal input level (dbm) input frequency (mhz) 51 48 45 42 39 36 33 30 27 24 21 18 15 12 9 6 3 0 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 40 c +25 c +85 c figure 30. main divider input sensitivity vs. frequency and temperature (i set = 164 m a; nf = 0; mod = 8; n = 853; v dd = 3.0 v)
philips semiconductors product data sa8027 2.5 ghz low voltage, low power rf fractional-n/if integer frequency synthesizer 2001 aug 21 18 typical performance characteristics (continued) sr02349 minimum signal input level (dbm) frequency (mhz) 42 39 36 33 30 27 24 21 18 15 12 9 6 3 0 0 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 2.6v 3.0v 3.6v figure 31. auxiliary divider input sensitivity vs. frequency and supply voltage (temp = 25 c; i set = 164 m a; divider ratio = 213) sr02350 miminum signal input level (dbm) frequency (mhz) 42 39 36 33 30 27 24 21 18 15 12 9 6 3 0 0 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 40 c +25 c +85 c figure 32. auxiliary divider input sensitivity vs. frequency and temperature (i set = 164 m a; divider ratio = 213; v dd = 3.0 v) sr02351 minimum signal input level (dbm) frequency (mhz) 30 27 24 21 18 15 12 9 6 3 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 2.6v 3.0v 3.6v figure 33. reference divider input sensitivity vs. frequency and supply voltage (temp = 25 c; i set = 164 m a; divider ratio = 682) sr02352 minimum signal input level (dbm) frequency (mhz) 30 27 24 21 18 15 12 9 6 3 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 40 c +25 c +85 c figure 34. reference divider input sensitivity vs. frequency and temperature (i set = 164 m a; divider ratio = 682; v dd = 3.0 v) sr02353 total current (ma) supply voltage (v) 6.00 6.50 7.00 7.50 8.00 8.50 9.00 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 40 c +25 c +85 c figure 35. total supply current vs. temperature (i set = 164 m a)
philips semiconductors product data sa8027 2.5 ghz low voltage, low power rf fractional-n/if integer frequency synthesizer 2001 aug 21 19 tssop20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1
philips semiconductors product data sa8027 2.5 ghz low voltage, low power rf fractional-n/if integer frequency synthesizer 2001 aug 21 20 hbcc24: plastic, heatsink bottom chip carrier; 24 terminals; body 4 x 4 x 0.65 mm sot564-1
philips semiconductors product data sa8027 2.5 ghz low voltage, low power rf fractional-n/if integer frequency synthesizer 2001 aug 21 21 notes
philips semiconductors product data sa8027 2.5 ghz low voltage, low power rf fractional-n/if integer frequency synthesizer 2001 aug 21 22 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . ? koninklijke philips electronics n.v. 2001 all rights reserved. printed in u.s.a. date of release: 09-01 document order number: 9397 750 08745

data sheet status [1] objective data preliminary data product data product status [2] development qualification production definitions this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the specification in any manner without notice. this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. changes will be communicated according to the customer product/process change notification (cpcn) procedure snw-sq-650a. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com.

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